1. Technical Field
This disclosure generally relates to integrated circuits, and more specifically relates to timing analysis of integrated circuit designs.
2. Background Art
The proliferation of modern electronics is due in large part to the development of the integrated circuit. Integrated circuits allow many different circuit elements to be implemented on a single chip. As technology advances, the number of circuit elements on a chip of a given size increases, enhancing the performance and reducing the cost of integrated circuits.
The design of integrated circuits is typically performed in three stages. The first stage is logic design, wherein the desired operation of the integrated circuit is defined. The second stage is logic synthesis, wherein the desired operation is translated into the required circuit elements for a given technology. The third stage is physical design, which assigns the placement of these elements and routing which creates the wire interconnect of these elements on the integrated circuit. Placement defines the location of the circuit elements on the integrated circuit. Routing defines interconnections between circuit elements.
At the logic synthesis stage, a static timing tool is typically used to perform a static timing analysis. Static timing analysis generally takes into account best-case and worst-case delays of various circuit elements, thereby generating a list of problems that need to be corrected. One common static timing tool developed by IBM is known as EinsTimer. EinsTimer is a sophisticated timing tool that performs static timing analysis on an integrated circuit design to identify potential timing problems with the design. EinsTimer includes sophisticated methods for performing the static timing analysis.
Static timing analysis tools typically operate based on technology rules and user assertions. For a sample design of a circuit, the circuit will have some delay as defined by the technology rules. User assertions define the performance target for the design. Known static timing analysis tools bind user assertions to a “clock” or “phase.” For example, the input of a design may expect a signal to arrive at time 100 if it is launched by clock A, but time 200 if launched by clock B. These different user assertions are applied at the same point and are differentiated by their clock. Known static timing analysis tools require clocks to be defined according to an arbitrary name. This can cause problems when two parts of the same design expect the same clock, but under different names. This can happen when a designer imports a logic block provided by a third party into a design. The design may have a clock named CLKA, but the third party logic block may have existing user assertions written in terms of a clock named CLKB. There are two solutions to this problem. The first is to rewrite the existing user assertions for the third party logic block to refer to CLKA instead of CLKB. This is not a viable solution because of the time required to rewrite all of the existing user assertions. In addition, if the third party supplier provides an updated set of user assertions, the effort to rewrite the user assertions will have to be repeated to take advantage of the updated user assertions. A second solution is for a designer to manually create a clock in the design named CLKB that mimics the characteristics of CLKA. However, it is common to have many hundreds of clocks in a design, which puts a significant burden on a designer to manually create many duplicate clocks that mimic the behavior of many other clocks. In addition, the process for manually defining duplicate clocks that mimic other real clocks is time-consuming and prone to user errors.